Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
Dynamic loadline handling optimizes operational voltages by dynamically adjusting an operating voltage based on the worst case current draw for a particular configuration. From a transition ordering perspective, a voltage increase is required for a core or other processor logic to exit a low power state, because an extra core being awake means higher worst case current (even though the voltage required at the gate has not increased). The result of this requirement is that low power state exits cannot proceed ahead of voltage increases from an ordering perspective. However, in certain situations, such as where a large voltage increase is under way, the low power state exit be undesirably delayed.